AMCC Becomes AppliedMicro—with the Focus on Low-Power Processing

RTC sat down recently with newly renamed AppliedMicro’s VP of Engineering, Vinay Ravuri, to discuss some of the challenges of producing more power-efficient, lower-cost silicon while retaining performance—a goal his company has publically committed to.


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Electricity—we’re using more of it and it’s costing more. And so much of it that we use is wasted, simply dissipated as heat, which requires even more electricity in the form of cooling systems and strategies. It is no great revelation to see that semiconductor manufacturers are well aware of this and are making huge efforts to reduce power consumption and increase efficiency. This results not only in lower costs but also helps bring embedded intelligence into ever smaller spaces in terms of applications—places where things like 32-bit CPUs would have been unimaginable only a short time ago.

Making a major commitment to focus on energy-efficient solutions for embedded computing is the 30-year-old company formerly known as Applied Micro Circuits Corporation (AMCC), which has renamed itself AppliedMicro (and redesigned its logo to have a green color). It has also divested itself of a division that it felt was not in line with the new focus. AppliedMicro sold its 3ware storage division to LSI so it could concentrate on its fabless business model. According to VP of Engineering, Vinay Ravuri, “One of the goals is to drive the company’s technology toward reducing energy consumption by as much as 50 percent, and that is better than the industry average.”

If power and heat dissipation are issues in small embedded devices, they are a huge and growing challenge in large installations like the data center. As the world moves to an all-IP communications infrastructure, we are looking at extremely rapid growth in global IP traffic, and this will be made even more extreme by the demand for high-performance connectivity to service the growing traffic in high-definition video (Figure 1). In addition, with a large portion of industrial Ethernet and long-haul networks moving to 10 Gbit/s, there will be increased demand for power-efficient transports such as OTN to handle legacy technologies such as SONET until the world transitions into an all-IP infrastructure. All this translates into increased electricity use and the opportunity to serve these markets, which is what AppliedMicro has decided to focus on. A snapshot of the company’s view of power consumption paths is shown in Figure 2.

Figure 1
Global IP growth by sectors 2009 – 2012 (source AppliedMicro)

Figure 2
Global IP growth by sectors 2009 – 2012 (source AppliedMicro)

Interestingly, they have decided on a fabless business model, which puts them in partnership and cooperative relationships with both customers and fab companies. Currently, AppliedMicro is working closely with Taiwan Semiconductor Manufacturing (TSMC) and has gone to a bulk CMOS process at 40nm. The company has also announced that it is targeting a 28nm process for many of its system-on-chip products, which are primarily based on the Power architecture. Such a strategy involves huge commitments on the part of fab partners, who must be deeply involved with the AppliedMicro’s process engineers. It also requires building the fab partner’s confidence to invest in the advanced equipment needed to support these smaller geometries and processes.

Of course, simply shrinking the geometry is not the whole solution of power reduction. It can even produce complications due to the fact that even reduced power consumption has less thermal mass to dissipate the heat that it does produce. According to Ravuri, “You can’t just marginally reduce the geometry and expect a huge power reduction. There are several other things you have to do.”

Among these “other things” are innovative circuit design and intelligent power management within the SoC. And here, of course, is where the details become a bit sketchy, because optimizing these technologies is what lies at the heart of AppliedMicro’s efforts. Despite all the publicity we’ve heard about intelligent power management for things like battery conservation, Ravuri doesn’t seem too impressed. “Typical processors in the past really didn’t pay much attention to power management,” he says. On the other hand, he notes, “You can build efficient processors and dissipate as much heat as possible but that doesn’t mean your processor is not being used. If it’s still running, it’s still consuming energy.”

Processors with different levels of sleep mode are, of course, fairly familiar, but Ravuri says there is no real standard way of using sleep modes. That would seem to imply that the developer is left on his or her own to figure out the optimal way of utilizing available sleep modes for any given application. Putting the CPU into too deep a mode may affect critical performance, while not putting it to sleep in certain situations might adversely affect power consumption.

These design challenges are certainly not going to go away, but Ravuri is announcing that AppliedMicro is taking a somewhat more hardware-centric approach to power management. This may be aided by the fact that the devices are SoC, which include the Power processor architecture plus other elements and peripheral circuits that would not be on-chip in the case of a general microprocessor. “We have these elements inside the device that software can control, but some of the intelligence is actually embedded within the hardware itself, which makes it easier,” he says.

Here again, the deep details are part of AppliedMicro’s “secret sauce,” but Ravuri did mention the example of energy-efficient Ethernet, which is a proposed IEEE standard 802.3az, so we may speculate that this example is the inspiration for other proprietary techniques being developed in-house by AppliedMicro. Energy-efficient Ethernet involves intelligent MAC hardware that can detect the load and automatically negotiate the link downward in cooperation with the peer. 

Of course, how low to negotiate and under which circumstances is still a design decision, as is how absolutely low you can go and not risk unacceptable packet loss when an application or the operating system decides to override the power saving mode. It will be interesting to see, once actual products are rolled out with hardware-based power management functionality, exactly what choices and techniques will be offered to system developers and the nature of the decisions they will then need to make to optimize power use and performance.

The strategy then is the combination of advances in process technology and basic circuit design plus innovative hardware design for control modes to manage power as well as to reduce it. And then there is the matter of performance—do we compromise things like clock speed to achieve power reduction? Ravuri’s short answer: “What would be the point of that?” Of course, that’s easier said than done.

So far, the only publically announced numbers for power/performance enhancements involve a single device, but are nonetheless significant. The 405EXr is a Power Architecture-based SoC device used in wireless LAN points and NAS storage systems. AppliedMicro has announced a reduction in worst-case power consumption from 3.5 watts to 2 watts—a drop of almost 40 percent. At the same time, the peak clock speed remains 533 MHz. Currently the company is migrating all customers for this product to the low-power version, and all new customers will receive that version as well.

We appear to be on the threshold of a general move to radically reduce the power consumption of silicon. The advent of the Intel Atom a few years ago based on that company’s 45nm geometry (soon to move to 32nm) has spread to other Intel product lines such as their multicore products. Another x86 player, VIA, is staking its turf in the low-power arena as well. As the learning curve advances, others are sure to follow because the system advantages can be tremendous.


AppliedMicro, Sunnyvale, CA. (408) 542-8600. [].

VIA Technologies, Fremont, CA. (510) 683-3300. [].