SDK Targeted for Designs Using PCI Express 3.0 Switches

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An upgraded and free software development kit (SDK) supports the PLX ExpressLane PCI Express (PCIe) Gen 3 switches. This suite of software tools works in conjunction with PLX’s on-chip diagnostic hardware, together called visionPAK. The SDK enables designers to get to market faster with instant access to internal chip registers, and offers diagnostic features as well as performance monitoring of an entire system’s performance, thus optimizing the usage of costly test equipment such as logic analyzers, traffic generators and high-speed oscilloscopes. 

Measuring the height and width quality of the SerDes eye, generating desired packets/traffic at line rate, injecting and counting errors, port utilization, and measuring performance are among the array of key features implemented in this multi-generation, backward-compatible SDK suite. Global designers continue to cite the cost-effectiveness of the PLX SDK in that it reduces the bottlenecks associated with expensive third-party analyzers and scopes and closes the loop on common buggy system issues. The ability to quickly debug systems in the lab while improving performance using the PLX SDK helps those designers streamline their designs. The SDK runs on Windows/Linux systems and connects to PLX devices through the host port or I2C interface provided on all PCIe Gen 2 and Gen 3 switches. 

Some of the additional key features of the PLX SDK beta version 6.4 include an updated Packet Generator tool, faster downloads because the SDK size has been reduced by half and special support for AHB register access as well as kernel drivers for PLX PCIe Gen 3 switches with on-chip DMA. There is a facility to compare register dump text files and a slave mode loopback for Gen 3 switches along with the ability to auto-detect requestor ID for setting up Non-Transparent Mode Address Translation. The suite also includes a Java-based PEX Device Editor GUI for Linux.

PLX Technology, Sunnyvale, CA. ((408) 774-9060. [].